Thin film transistors ("TFTs") are often used in place of load resistors in SRAMs of the type over the 1M class. TFTs are also widely used in liquid crystal displays as switching elements for switching video data signals of the pixel regions.
In a high quality SRAM, a thin film transistor has a reduced and relatively low off current and an increased and relatively high on current. SRAMs with TFTs having these characteristics have reduced power consumption and improved memory capabilities. Based on the foregoing principle, studies for improving the on/off current ratio are actively underway.
A conventional method for improving the on/off current ratio can be described with reference to FIGS. 1(a)-1(d). Illustrated in FIGS. 1(a)-1(d) are sections of a conventional fabricating process for a thin film transistor. This process uses a bottom gate as a nucleus and results in the growth of larger grain sizes based on solid state grain growth of the silicon body. The grain is grown by heat treatment at about 600 deg. C. for a relatively long period of time, such as 24 hours.
As shown in FIG. 1(a), a gate electrode 2 is formed by depositing polysilicon on an insulating substrate 1 or on an insulating film, and patterning the polysilicon with a photoetching process using a gate mask. Then, as shown in FIG. 1(b), a layer of gate insulation film 3 and a body of polysilicon 4 are deposited successively over the surface of the gate electrode 2 and the substrate 1 using a chemical vapor deposition method. Thereafter, the grain size of the polysilicon body is grown larger using the solid state grain growth method by heat treating the polysilicon body at about 600 deg. C. for a relatively long time, such as about 24 hours.
As shown in FIG. 1(c), the channel region is masked by depositing a photosensitive film 5 on the body of polysilicon 4 and carrying out exposure and development processes. The channel region is masked and formed so that the source region 6a overlaps the gate electrode 2, and the drain region 6b is offset with respect to the gate electrode 2. Then, as shown in FIG. 1(d), by injecting P-type impurity ions e.g., (BF.sub.2), into the exposed body of polysilicon 4, and forming source/drain regions 6a and 6b, a conventional P-type MOS thin film transistor can be completed. The various regions of the transistor shown in FIG. 1(d) are indicated by the following relation: a: source region, b: channel region, c: drain region.
However, the conventional thin film transistor described above has a number of deficiencies. First, the definition of the channel region together with the offset region using the photomask process complicates the process, makes reproduction difficult and greatly increases variation of the off current depending on degree of the alignment. The reliability of the thin film transistor is thereby degraded.
Second, since the position of the channel is relatively far from the gate electrode, the channel may not be completely cut off or inverted. Leakage current can therefore occur, reducing the on current.
Third, because the channel of the thin film transistor has a planar arrangement, if the cell size becomes smaller, the length of the channel also becomes shorter. This shorter channel results in increased leakage current, and thereby limits the level of integration that can be obtained.